1. Field of the Invention
The present invention relates to a data processing apparatus and method for evaluating condition codes used to determine whether conditional instructions are to be executed.
2. Description of the Prior Art
When processing a sequence of instructions within a data processing apparatus, it is often the case that at least some of those instructions are conditional instructions that are conditionally executed dependent on the state of a number of condition codes. A set of condition codes will typically be maintained by the processor, with the state of those condition codes being set by execution of condition code setting instructions.
A conditional instruction can then specify one of a number of conditions that need to exist at the time of execution of that conditional instruction in order for that conditional instruction to be executed. Each condition will equate to a particular state of one or more of the condition codes, and accordingly by evaluating the condition codes at the time of execution of a conditional instruction, it can be determined whether that instruction should be executed or not.
It is common for processors used to execute sequences of instructions to have a pipelined architecture consisting of multiple pipeline stages, this enabling a plurality of instructions to be in the process of being executed by the processor at any point in time. Each instruction passes through the various pipeline stages of the processor during its execution, typically resulting in the final pipeline stage performing an update of the state of the data processing apparatus in order to complete execution of that instruction. For example, the update of the state of the data processing apparatus may involve an update of certain registers of a register bank accessible by the processor in order to reflect the result of execution of that instruction.
In order to correctly evaluate the condition codes in order to determine whether a particular conditional instruction should be executed, it is first necessary to ensure that any condition code setting instructions ahead of that conditional instruction in the pipeline have already been executed, since otherwise it cannot be determined that the correct condition codes have been evaluated. This typically means that a conditional instruction will need to pass through a significant number of pipeline stages of the processor before the condition codes can be evaluated. This can significantly impact the performance of the data processing apparatus.
For example, some of said conditional instructions may be branch instructions that cause a change in instruction flow, and clearly not being able to confirm whether the branch instruction will or will not be executed until that instruction has passed through a significant portion of the pipeline can significantly affect the time taken to retrieve and process the next instruction following such a branch instruction. As another example, some of the conditional instructions may be conditional coprocessor instructions that are to be executed by a coprocessor. Typically, the coprocessor instruction will routed to the coprocessor as soon as it is determined that it is a coprocessor instruction, with that coprocessor instruction also being routed through the main pipelined processor to enable the condition codes to be evaluated. If the condition code evaluation cannot take place until the instruction has passed through a number of the pipeline stages, it may then be necessary to cancel the coprocessor instruction midway through its execution by the coprocessor. However, designing a coprocessor that can support the cancellation of an instruction midway through execution complicates the design. In particular, it makes the register scoreboard logic more complex. Further, it can complicate coprocessor interface designs since conditional coprocessor instructions (if not to be executed) must be removed from both the main pipeline and the coprocessor, and the pipelines need to remain in synchronisation.
Accordingly, it would be desirable to provide a technique for evaluating condition codes which alleviates the above described problems.